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Memory architecture
Results: 1714

#	Item
831	Attacking SMM Memory via Intel® CPU Cache Poisoning Rafal Wojtczuk [removed] Joanna Rutkowska [removed] Add to Reading List Source URL: invisiblethingslab.com Language: English - Date: 2009-03-19 09:49:58 Computer memory Programming language implementation Memory type range register Trusted Execution Technology CPU cache Protected mode Joanna Rutkowska X86 Computer architecture Computing System Management Mode
832	Microsoft PowerPoint - present_isca0 [Compatibility Mode] Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2011-01-05 13:37:23 Honda P series Josep Torrellas Computing Computer architecture Parallel computing Memory disambiguation
833	21264/EV68CB and[removed]EV68DC Hardware Reference Manual Part Number: DS–0031C–TE This manual is directly derived from the internal[removed]EV68CB and[removed]EV68DC Add to Reading List Source URL: download.majix.org Language: English - Date: 2013-01-10 05:02:21 Instruction set architectures DEC Alpha Computer memory PALcode CPU cache ARM architecture Processor register Instruction set Computer architecture Computer hardware Central processing unit
834	A Framework for Dynamic Energy Efficiency and Temperature Management Michael Huang , Jose Renau , Seung-Moon Yoo , and Josep Torrellas Department of Computer Science Department of Electrical and Computer Engineering Univ Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-27 12:19:17 Cache Central processing unit Computer architecture Microprocessors CPU cache Multi-core processor Parallel computing Dynamic random-access memory Computer hardware Computing Computer memory
835	Using Register Lifetime Predictions to Protect Register Files Against Soft Errors∗ Pablo Montesinos, Wei Liu and Josep Torrellas Department of Computer Science University of Illinois at Urbana-Champaign {pmontesi, liuw Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2007-04-07 18:15:20 Central processing unit Computer memory Register renaming Register file CPU cache Branch predictor Parity bit 64-bit Processor register Computer hardware Computer architecture Computing
836	Alpha 21066A Microprocessor Evaluation Board (EB66+) User’s Guide Order Number: EC–QDVCB–TE Revision/Update Information: Add to Reading List Source URL: download.majix.org Language: English - Date: 2013-01-10 05:04:39 Computer architecture Conventional PCI PCI Express Alpha 21064 Industry Standard Architecture Expansion card Bus Flash memory Interrupt Computer hardware Computer buses Computing
837	DECchip[removed]Core Logic Chipset Technical Reference Manual Order Number: EC–QE18B–TE Revision/Update Information: Add to Reading List Source URL: download.majix.org Language: English - Date: 2013-01-10 05:04:22 Computer buses Computer memory Central processing unit Instruction set architectures Conventional PCI PCI configuration space DEC Alpha PCI Express VAX Computer hardware Computer architecture Computing
838	Digital Semiconductor[removed]Core Logic Chip Technical Reference Manual Order Number: EC–R12GB–TE Revision/Update Information: This is a revised, preliminary Add to Reading List Source URL: download.majix.org Language: English - Date: 2013-01-10 05:03:38 Computing Conventional PCI PCI configuration space PCI Express Control register Interrupt DEC Alpha Direct memory access PCI-X Computer hardware Computer architecture Computer buses
839	Vulcan: Hardware Support for Detecting Sequential Consistency Violations Dynamically ∗ Abdullah Muzahid† , Shanxiang Qi, and Josep Torrellas University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu Abstra Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2012-11-04 16:19:00 Computing Central processing unit Computer architecture CPU cache Cache Parallel computing MSI protocol False sharing Cache coherency Computer memory Computer hardware
840	Rapid Prototyping in Architecture Research using Hardware Hooks in COTS Systems Smruti R. Sarangi, Brian Greskamp and Josep Torrellas Department of Computer Science, University of Illinois http://iacoma.cs.uiuc.edu Abstr Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2006-06-25 20:28:19 Central processing unit Computer memory Northbridge Hardware performance counter P5 Hyper-threading Intel Microarchitecture Memory address Computer hardware Computer architecture Computing

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